Analysis and design of a buffer for high performance LDO Click Copy

Analysis and design of a buffer for high performance LDO


[1] Buss D. Technology in the internet age[C].IEEE International Solid State Circuits Conference on Digest of Technical Papers. San Francisco:CA,2002.
[2] Lee Bang S. Understanding the terms and definitions of LDO voltage regulators[Z]. Texas: Texas Instruments Inc, 1999.
[3] Rincon-Mora G A,Allen P E.A low-voltage, low quiescent current, low drop-out regulator[J]. IEEE Solid-State Circuits,1998,33(1):36-44.
[4] Stanescu C. Buffer stage for fast response LDO[J]. IEEE Custom Integrated Circuits,2006,18(6):83-86.
[5] Chen Jiann-jong,Hwang Yuh-Shyan. A capacitor-free fast-transient-response LDO with dual-loop controlled paths[J]. IEEE Asian Solid-State Circuits,2007,13(5):23-32.
[6] Ahuja B K. An improved frequency compensation technique for CMOS operational amplifers[J]. IEEE Solid-State Circuits,1983,18(6):29-33.
[7] Lu Sao-Hung,Huang Wei-Jen.A fast-recovery low dropout linear regulator for any-type output capacitors[J]. IEEE Solid-State Circuits,2005,8(6):497-500.
[8] Rincon-Mora G A. Current efficient Low voltage Low drop-out Regulators[D]. Georgia: Georgia Institute of Technology,1996.
[9] Razavi B. Design of Analog CMOS Integrated Circuits[M]. New York: McGraw-Hill Inc. 2001.
[10]Gray P R, Hurst P J,Meyer R G. Analysis and Design of Analog Integrated Circuits[M]. New York: John Wiley & Sons Inc.,2005.


基金项目: 陕西省科学技术研究发展计划项目(2008K04-16); 西安市科技攻关项目(YF07020) 通讯作者: 张允武(1987-),男,江苏南通人,硕士研究生,主要从事集成电路设计的研究工作.